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authorLinus Torvalds <torvalds@linux-foundation.org>2012-07-23 16:08:40 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2012-07-23 16:08:40 -0700
commit5e512d0785e67d9ff41ee4af39bb71fc6161d5c9 (patch)
tree5b0decd6d5b11138a6614c4f7b17592aa76520c6 /drivers/clk
parent451ce7f9cf2d17e34d5d64b76cac047a2a1a3b89 (diff)
parent233de298cb44e7dd300cd68f5abd7f1a75561fd5 (diff)
downloadlinux-5e512d0785e67d9ff41ee4af39bb71fc6161d5c9.tar.bz2
Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull arm soc-specific updates from Arnd Bergmann: "This is stuff that does not fit well into another category and in particular is not related to a particular board. The largest part in here is extending the am33xx support in the omap platform." Fix up trivial conflicts in arch/arm/mach-{imx/mach-mx35_3ds.c, tegra/Makefile} * tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (74 commits) ARM: LPC32xx: Add PWM support ARM: LPC32xx: Add PWM clock ARM: LPC32xx: Set system serial based on cpu unique id ARM: vexpress: Config option for early printk console ARM: vexpress: Add Device Tree for V2P-CA15_CA7 core tile ARM: vexpress: Convert V2P-CA15 Device Tree to 64 bit addresses ARM: vexpress: Add fixed regulator for SMSC ARM: vexpress: Add missing SP804 interrupt in motherboard's DTS files ARM: vexpress: Initial common clock support ARM: SAMSUNG: Introduce Kconfig variable for Samsung custom clk API ARM: EXYNOS: Add missing static storage class specifier in pmu.c file ARM: EXYNOS: Make combiner_init function static ARM: EXYNOS: Update HSOTG PHY clock setting for EXYNOS4X12 ARM: versatile: Make plat-versatile clock optional ARM: vexpress: Check master site in daughterboard's sysctl operations ARM: vexpress: remove automatic errata workaround selection ARM: LPC32xx: Adjust to pl08x DMA interface changes ARM: EXYNOS: Clear SYS_WDTRESET bit to use watchdog reset ARM: imx: fix mx51 ehci setup errors ARM: imx: make ehci power/oc polarities configurable ...
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/Makefile1
-rw-r--r--drivers/clk/clk-nomadik.c47
2 files changed, 48 insertions, 0 deletions
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index b9a5158a30b1..26b6b92942e1 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -3,5 +3,6 @@ obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o
obj-$(CONFIG_COMMON_CLK) += clk.o clk-fixed-rate.o clk-gate.o \
clk-mux.o clk-divider.o clk-fixed-factor.o
# SoCs specific
+obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o
obj-$(CONFIG_ARCH_MXS) += mxs/
obj-$(CONFIG_PLAT_SPEAR) += spear/
diff --git a/drivers/clk/clk-nomadik.c b/drivers/clk/clk-nomadik.c
new file mode 100644
index 000000000000..517a8ff7121e
--- /dev/null
+++ b/drivers/clk/clk-nomadik.c
@@ -0,0 +1,47 @@
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/clk-provider.h>
+
+/*
+ * The Nomadik clock tree is described in the STN8815A12 DB V4.2
+ * reference manual for the chip, page 94 ff.
+ */
+
+void __init nomadik_clk_init(void)
+{
+ struct clk *clk;
+
+ clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
+ clk_register_clkdev(clk, "apb_pclk", NULL);
+ clk_register_clkdev(clk, NULL, "gpio.0");
+ clk_register_clkdev(clk, NULL, "gpio.1");
+ clk_register_clkdev(clk, NULL, "gpio.2");
+ clk_register_clkdev(clk, NULL, "gpio.3");
+ clk_register_clkdev(clk, NULL, "rng");
+
+ /*
+ * The 2.4 MHz TIMCLK reference clock is active at boot time, this is
+ * actually the MXTALCLK @19.2 MHz divided by 8. This clock is used
+ * by the timers and watchdog. See page 105 ff.
+ */
+ clk = clk_register_fixed_rate(NULL, "TIMCLK", NULL, CLK_IS_ROOT,
+ 2400000);
+ clk_register_clkdev(clk, NULL, "mtu0");
+ clk_register_clkdev(clk, NULL, "mtu1");
+
+ /*
+ * At boot time, PLL2 is set to generate a set of fixed clocks,
+ * one of them is CLK48, the 48 MHz clock, routed to the UART, MMC/SD
+ * I2C, IrDA, USB and SSP blocks.
+ */
+ clk = clk_register_fixed_rate(NULL, "CLK48", NULL, CLK_IS_ROOT,
+ 48000000);
+ clk_register_clkdev(clk, NULL, "uart0");
+ clk_register_clkdev(clk, NULL, "uart1");
+ clk_register_clkdev(clk, NULL, "mmci");
+ clk_register_clkdev(clk, NULL, "ssp");
+ clk_register_clkdev(clk, NULL, "nmk-i2c.0");
+ clk_register_clkdev(clk, NULL, "nmk-i2c.1");
+}