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authorTero Kristo <t-kristo@ti.com>2018-02-23 14:29:19 +0200
committerTero Kristo <t-kristo@ti.com>2018-03-08 12:14:43 +0200
commitc083dc5f3738d394223baa0f90705397b0844acd (patch)
tree97d9c21df25946ce0bcc0ccb37452b97d32c34f8 /drivers/clk/ti
parent49159a9dc3da83f17be00acbc7b2ab84ffec1aa7 (diff)
downloadlinux-c083dc5f3738d394223baa0f90705397b0844acd.tar.bz2
clk: ti: am33xx: add set-rate-parent support for display clkctrl clock
Display driver assumes it can use clk_set_rate for the display clock via set-rate-parent mechanism, so add the flag for this to it. Signed-off-by: Tero Kristo <t-kristo@ti.com> Reported-by: Jyri Sarha <jsarha@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Tested-by: Jyri Sarha <jsarha@ti.com>
Diffstat (limited to 'drivers/clk/ti')
-rw-r--r--drivers/clk/ti/clk-33xx.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/ti/clk-33xx.c b/drivers/clk/ti/clk-33xx.c
index 612491a26070..12e0a2d19911 100644
--- a/drivers/clk/ti/clk-33xx.c
+++ b/drivers/clk/ti/clk-33xx.c
@@ -45,7 +45,7 @@ static const struct omap_clkctrl_bit_data am3_gpio4_bit_data[] __initconst = {
static const struct omap_clkctrl_reg_data am3_l4_per_clkctrl_regs[] __initconst = {
{ AM3_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk", "cpsw_125mhz_clkdm" },
- { AM3_LCDC_CLKCTRL, NULL, CLKF_SW_SUP, "lcd_gclk", "lcdc_clkdm" },
+ { AM3_LCDC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "lcd_gclk", "lcdc_clkdm" },
{ AM3_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "usbotg_fck", "l3s_clkdm" },
{ AM3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
{ AM3_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_div2_ck", "l3_clkdm" },