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authorPeter De Schrijver <pdeschrijver@nvidia.com>2017-07-25 13:34:06 +0300
committerStephen Boyd <sboyd@codeaurora.org>2017-08-23 15:59:15 -0700
commitbc7b34a2fb78661b2980d949aad8edc39c253e3a (patch)
treea518f04fca7e3146d3ba85d0f49550cb737155b1 /drivers/clk/tegra
parente34e69cc866a26ec42be789a49ea6174ddc801ca (diff)
downloadlinux-bc7b34a2fb78661b2980d949aad8edc39c253e3a.tar.bz2
clk: tegra: Init cfg structure in _get_pll_mnp
Not all fields are read from the hw depending on the PLL type. Make sure the other fields are 0 by clearing the structure beforehand to prevent users such as the rate re-calculation code from using bogus values. Based on work by Alex Frid <afrid@nvidia.com> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/tegra')
-rw-r--r--drivers/clk/tegra/clk-pll.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index fbd8726213ab..1c36b8a72bd2 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -690,6 +690,8 @@ static void _get_pll_mnp(struct tegra_clk_pll *pll,
struct tegra_clk_pll_params *params = pll->params;
struct div_nmp *div_nmp = params->div_nmp;
+ *cfg = (struct tegra_clk_pll_freq_table) { };
+
if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
(pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {