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| author | Thierry Reding <treding@nvidia.com> | 2015-03-23 10:52:45 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2015-04-10 16:04:20 +0200 |
| commit | 699b477a0d3a5bc68034a1520a4337ea0a20f63b (patch) | |
| tree | cbd74f6791b022d63f8b556b042afde65f006d18 /drivers/clk/tegra/clk.h | |
| parent | 5e43e259171e1eee8bc074d9c44be434e685087b (diff) | |
| download | linux-699b477a0d3a5bc68034a1520a4337ea0a20f63b.tar.bz2 | |
clk: tegra: Add peripheral registers for bank Y
Tegra210 has an extra bank of peripheral clock registers. Add it to the
generic peripheral clock code.
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk.h')
0 files changed, 0 insertions, 0 deletions