diff options
| author | Peter De Schrijver <pdeschrijver@nvidia.com> | 2013-04-03 17:40:37 +0300 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2013-04-04 16:10:38 -0600 |
| commit | dd93587be8dc8acf23a0d8a23efc74a91d8f0dfe (patch) | |
| tree | 10a49812292f09a9b5d5d33fb09cc895dfb16b32 /drivers/clk/tegra/clk.h | |
| parent | dba4072a4a20b2986562cced98ce04a887614528 (diff) | |
| download | linux-dd93587be8dc8acf23a0d8a23efc74a91d8f0dfe.tar.bz2 | |
clk: tegra: Add TEGRA_PLL_BYPASS flag
Not all PLLs in Tegra114 have a bypass bit. Adapt the common code to only use
this bit when available.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk.h')
| -rw-r--r-- | drivers/clk/tegra/clk.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index b9691ddcbd9b..fff520ae72fc 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -184,6 +184,7 @@ struct tegra_clk_pll_params { * TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling. * TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the * base register. + * TEGRA_PLL_BYPASS - PLL has bypass bit */ struct tegra_clk_pll { struct clk_hw hw; @@ -213,6 +214,7 @@ struct tegra_clk_pll { #define TEGRA_PLL_FIXED BIT(6) #define TEGRA_PLLE_CONFIGURE BIT(7) #define TEGRA_PLL_LOCK_MISC BIT(8) +#define TEGRA_PLL_BYPASS BIT(9) extern const struct clk_ops tegra_clk_pll_ops; extern const struct clk_ops tegra_clk_plle_ops; |