diff options
| author | Rhyland Klein <rklein@nvidia.com> | 2015-06-18 17:28:36 -0400 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2015-12-17 13:37:56 +0100 |
| commit | 6b301a059eb2ebed1b12a900e3b21a38e48dd410 (patch) | |
| tree | 52cb25fb0297134f7f137b41bf77941dd7f4f585 /drivers/clk/tegra/clk.h | |
| parent | 139fd30943c3c8ed76d0ce08ff711cfff3b118ec (diff) | |
| download | linux-6b301a059eb2ebed1b12a900e3b21a38e48dd410.tar.bz2 | |
clk: tegra: Add support for Tegra210 clocks
Implement clock support for Tegra210.
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk.h')
| -rw-r--r-- | drivers/clk/tegra/clk.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index cb9670ee22a6..4dbcfaec576a 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -242,6 +242,7 @@ struct tegra_clk_pll; * it may be more accurate (especially if SDM present) * TEGRA_PLLMB - PLLMB has should be treated similar to PLLM. This * flag indicated that it is PLLMB. + * TEGRA_PLL_VCO_OUT - Used to indicate that the PLL has a VCO output */ struct tegra_clk_pll_params { unsigned long input_min; @@ -307,6 +308,7 @@ struct tegra_clk_pll_params { #define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10) #define TEGRA_MDIV_NEW BIT(11) #define TEGRA_PLLMB BIT(12) +#define TEGRA_PLL_VCO_OUT BIT(13) /** * struct tegra_clk_pll - Tegra PLL clock @@ -766,5 +768,6 @@ typedef void (*tegra_clk_apply_init_table_func)(void); extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table; int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll); u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate); +int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div); #endif /* TEGRA_CLK_H */ |