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| author | Yangtao Li <tiny.windzz@gmail.com> | 2018-12-26 08:29:02 -0500 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2018-12-28 11:29:06 -0800 |
| commit | 7f9705beeb3759e69165e7aff588f6488ff6c1ac (patch) | |
| tree | 3801028ce2c6635bf53179e1de65da4525b504b0 /drivers/clk/socfpga/clk-pll-a10.c | |
| parent | 2274d8001fbb5e1942fbcab5ad2eb15553b09ed2 (diff) | |
| download | linux-7f9705beeb3759e69165e7aff588f6488ff6c1ac.tar.bz2 | |
clk: socfpga: fix refcount leak
The of_find_compatible_node() returns a node pointer with refcount
incremented, but there is the lack of use of the of_node_put() when
done. Add the missing of_node_put() to release the refcount.
Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
Fixes: 5343325ff3dd ("clk: socfpga: add a clock driver for the Arria 10 platform")
Fixes: a30d27ed739b ("clk: socfpga: fix clock driver for 3.15")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/socfpga/clk-pll-a10.c')
| -rw-r--r-- | drivers/clk/socfpga/clk-pll-a10.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/socfpga/clk-pll-a10.c b/drivers/clk/socfpga/clk-pll-a10.c index 35fabe1a32c3..269467e8e07e 100644 --- a/drivers/clk/socfpga/clk-pll-a10.c +++ b/drivers/clk/socfpga/clk-pll-a10.c @@ -95,6 +95,7 @@ static struct clk * __init __socfpga_pll_init(struct device_node *node, clkmgr_np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr"); clk_mgr_a10_base_addr = of_iomap(clkmgr_np, 0); + of_node_put(clkmgr_np); BUG_ON(!clk_mgr_a10_base_addr); pll_clk->hw.reg = clk_mgr_a10_base_addr + reg; |