diff options
| author | Yadwinder Singh Brar <yadi.brar@samsung.com> | 2013-06-11 15:01:12 +0530 |
|---|---|---|
| committer | Mike Turquette <mturquette@linaro.org> | 2013-08-02 13:22:09 -0700 |
| commit | 3ff6e0d8d64d594a551b5c4904e4b617bf7eee22 (patch) | |
| tree | f0eaf7340c495e131a1b1c2e083b1af224f434af /drivers/clk/samsung/clk.h | |
| parent | 5ca8fbd8d1b2650608d0c79bdf5e3f643a2f10e3 (diff) | |
| download | linux-3ff6e0d8d64d594a551b5c4904e4b617bf7eee22.tar.bz2 | |
clk: samsung: Add support to register rate_table for samsung plls
This patch defines a common rate_table which will contain recommended p, m, s,
k values for supported rates that needs to be changed for changing
corresponding PLL's rate.
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk/samsung/clk.h')
| -rw-r--r-- | drivers/clk/samsung/clk.h | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h index 4e83e521fe7d..b3f2532823d5 100644 --- a/drivers/clk/samsung/clk.h +++ b/drivers/clk/samsung/clk.h @@ -283,10 +283,12 @@ struct samsung_pll_clock { int con_offset; int lock_offset; enum samsung_pll_type type; + const struct samsung_pll_rate_table *rate_table; const char *alias; }; -#define __PLL(_typ, _id, _dname, _name, _pname, _flags, _lock, _con, _alias) \ +#define __PLL(_typ, _id, _dname, _name, _pname, _flags, _lock, _con, \ + _rtable, _alias) \ { \ .id = _id, \ .type = _typ, \ @@ -296,16 +298,17 @@ struct samsung_pll_clock { .flags = CLK_GET_RATE_NOCACHE, \ .con_offset = _con, \ .lock_offset = _lock, \ + .rate_table = _rtable, \ .alias = _alias, \ } -#define PLL(_typ, _id, _name, _pname, _lock, _con) \ +#define PLL(_typ, _id, _name, _pname, _lock, _con, _rtable) \ __PLL(_typ, _id, NULL, _name, _pname, CLK_GET_RATE_NOCACHE, \ - _lock, _con, NULL) + _lock, _con, _rtable, _name) -#define PLL_A(_typ, _id, _name, _pname, _lock, _con, _alias) \ +#define PLL_A(_typ, _id, _name, _pname, _lock, _con, _alias, _rtable) \ __PLL(_typ, _id, NULL, _name, _pname, CLK_GET_RATE_NOCACHE, \ - _lock, _con, _alias) + _lock, _con, _rtable, _alias) extern void __init samsung_clk_init(struct device_node *np, void __iomem *base, unsigned long nr_clks, unsigned long *rdump, |