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author | Stephen Boyd <sboyd@codeaurora.org> | 2017-10-05 16:52:59 -0700 |
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committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-10-05 16:52:59 -0700 |
commit | 0a4e632b6f9d1ccabe3e9507814184cd34ff3f31 (patch) | |
tree | 159fb3f5e032d119228ff07e1478f57887da58a5 /drivers/clk/samsung/clk-exynos4.c | |
parent | e7cc33358a88e0a0949370ada47144c11c2aa290 (diff) | |
parent | 5dcbeca615ef12047a5f4097b91030cbf995b1d2 (diff) | |
download | linux-0a4e632b6f9d1ccabe3e9507814184cd34ff3f31.tar.bz2 |
Merge branch 'clk-fixes' into clk-next
* clk-fixes:
clk: samsung: exynos4: Enable VPLL and EPLL clocks for suspend/resume cycle
Diffstat (limited to 'drivers/clk/samsung/clk-exynos4.c')
-rw-r--r-- | drivers/clk/samsung/clk-exynos4.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index e40b77583c47..d8d3cb67b402 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -294,6 +294,18 @@ static const struct samsung_clk_reg_dump src_mask_suspend_e4210[] = { #define PLL_ENABLED (1 << 31) #define PLL_LOCKED (1 << 29) +static void exynos4_clk_enable_pll(u32 reg) +{ + u32 pll_con = readl(reg_base + reg); + pll_con |= PLL_ENABLED; + writel(pll_con, reg_base + reg); + + while (!(pll_con & PLL_LOCKED)) { + cpu_relax(); + pll_con = readl(reg_base + reg); + } +} + static void exynos4_clk_wait_for_pll(u32 reg) { u32 pll_con; @@ -315,6 +327,9 @@ static int exynos4_clk_suspend(void) samsung_clk_save(reg_base, exynos4_save_pll, ARRAY_SIZE(exynos4_clk_pll_regs)); + exynos4_clk_enable_pll(EPLL_CON0); + exynos4_clk_enable_pll(VPLL_CON0); + if (exynos4_soc == EXYNOS4210) { samsung_clk_save(reg_base, exynos4_save_soc, ARRAY_SIZE(exynos4210_clk_save)); |