diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-09-18 10:55:29 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-09-25 08:55:56 +0200 |
| commit | 5915838b7a4fa6bd6819819de11bfc30a4323ad9 (patch) | |
| tree | 103ace63bdd797157399df6228b24d1c0cde750b /drivers/clk/renesas | |
| parent | 7c0043c0a48c18fccd43e5cd9f45751316564647 (diff) | |
| download | linux-5915838b7a4fa6bd6819819de11bfc30a4323ad9.tar.bz2 | |
clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment
PLL0 runs at 4.8 GHz, i.e. EXTAL x 100.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'drivers/clk/renesas')
| -rw-r--r-- | drivers/clk/renesas/r8a77990-cpg-mssr.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c index 7e000d070589..9eb80180eea0 100644 --- a/drivers/clk/renesas/r8a77990-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c @@ -250,8 +250,8 @@ static const unsigned int r8a77990_crit_mod_clks[] __initconst = { /* * MD19 EXTAL (MHz) PLL0 PLL1 PLL3 *-------------------------------------------------------------------- - * 0 48 x 1 x100/4 x100/3 x100/3 - * 1 48 x 1 x100/4 x100/3 x58/3 + * 0 48 x 1 x100/1 x100/3 x100/3 + * 1 48 x 1 x100/1 x100/3 x58/3 */ #define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19) |