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| author | Takeshi Kihara <takeshi.kihara.df@renesas.com> | 2018-04-20 21:27:43 +0900 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-04-24 09:54:34 +0200 |
| commit | 9a31fa395c19d5873190bf84c8192f5799861342 (patch) | |
| tree | d25ec2caaa8170fedaf03cc6a8eaa4bad625ac65 /drivers/clk/renesas/renesas-cpg-mssr.c | |
| parent | a34f778cb89a8554a5d1f5a75b297c07c672afce (diff) | |
| download | linux-9a31fa395c19d5873190bf84c8192f5799861342.tar.bz2 | |
clk: renesas: Add r8a77990 CPG Core Clock Definitions
This patch adds all R-Car E3 Clock Pulse Generator Core Clock Outputs.
Note that internal CPG clocks (S0, S1, S2, S3, SDSRC, POST3) are not
included, as they are used as internal clock sources only, and never
referenced from DT.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[shimoda: add SPDX-License-Identifier]
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas/renesas-cpg-mssr.c')
0 files changed, 0 insertions, 0 deletions