diff options
author | Abhishek Sahu <absahu@codeaurora.org> | 2017-12-13 19:55:32 +0530 |
---|---|---|
committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-12-21 16:03:19 -0800 |
commit | f933d383df6b42e3262426d35593f18ff21aad57 (patch) | |
tree | 2215a4f453fbc6e75c4966bdd807b91970c787b6 /drivers/clk/qcom/clk-regmap-divider.c | |
parent | 23c68cc9683efbd08457f06fb5eacd7c8616dfae (diff) | |
download | linux-f933d383df6b42e3262426d35593f18ff21aad57.tar.bz2 |
clk: qcom: add read-only divider operations
Some of the divider settings are preconfigured and should not
be changed by the clock framework during frequency change. This
patch adds the read-only divider operation for QCOM dividers
which is equivalent to generic divider operations in
'commit 79c6ab509558 ("clk: divider: add CLK_DIVIDER_READ_ONLY flag")'.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/qcom/clk-regmap-divider.c')
-rw-r--r-- | drivers/clk/qcom/clk-regmap-divider.c | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/drivers/clk/qcom/clk-regmap-divider.c b/drivers/clk/qcom/clk-regmap-divider.c index 53484912301e..6cf9005fb8c6 100644 --- a/drivers/clk/qcom/clk-regmap-divider.c +++ b/drivers/clk/qcom/clk-regmap-divider.c @@ -23,6 +23,29 @@ static inline struct clk_regmap_div *to_clk_regmap_div(struct clk_hw *hw) return container_of(to_clk_regmap(hw), struct clk_regmap_div, clkr); } +static long div_round_ro_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct clk_regmap_div *divider = to_clk_regmap_div(hw); + struct clk_regmap *clkr = ÷r->clkr; + u32 div; + struct clk_hw *hw_parent = clk_hw_get_parent(hw); + + regmap_read(clkr->regmap, divider->reg, &div); + div >>= divider->shift; + div &= BIT(divider->width) - 1; + div += 1; + + if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { + if (!hw_parent) + return -EINVAL; + + *prate = clk_hw_round_rate(hw_parent, rate * div); + } + + return DIV_ROUND_UP_ULL((u64)*prate, div); +} + static long div_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { @@ -68,3 +91,9 @@ const struct clk_ops clk_regmap_div_ops = { .recalc_rate = div_recalc_rate, }; EXPORT_SYMBOL_GPL(clk_regmap_div_ops); + +const struct clk_ops clk_regmap_div_ro_ops = { + .round_rate = div_round_ro_rate, + .recalc_rate = div_recalc_rate, +}; +EXPORT_SYMBOL_GPL(clk_regmap_div_ro_ops); |