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| author | Abhishek Sahu <absahu@codeaurora.org> | 2017-09-28 23:20:41 +0530 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-12-13 13:45:31 -0800 |
| commit | 1e859d3e03f0ac97d15e1952bddda4b29de1c71c (patch) | |
| tree | 5ba5a79a34e0d4e8b3b7b5ef2e7ddab6428a153f /drivers/clk/qcom/clk-alpha-pll.h | |
| parent | 28d3f06e56baa9c6e2c8e1d9e5fd663138c08b92 (diff) | |
| download | linux-1e859d3e03f0ac97d15e1952bddda4b29de1c71c.tar.bz2 | |
clk: qcom: fix 16 bit alpha support calculation
The alpha value calculation has been written for 40-bit alpha
values which doesn't work work properly for 16-bit ones. The
alpha value is calculated on the basis of ALPHA_BITWIDTH to make
the computation easy for 40 bit alpha. After calculating the 32
bit alpha, it is converted to 40 bit alpha by making lower bits
zero. But if actual alpha register width is less than
ALPHA_BITWIDTH, then the actual width can be used for
calculation. This also means, during the 40 bit alpha pll set
rate path, the lower alpha register is not configured
Change the code to calculate the rate and register values from
'alpha_width' instead of hard-coding it so that it can work for
the different widths that are supported.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/qcom/clk-alpha-pll.h')
| -rw-r--r-- | drivers/clk/qcom/clk-alpha-pll.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index ef7c75effbfe..18c0c3eff855 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -59,7 +59,6 @@ struct clk_alpha_pll { const struct pll_vco *vco_table; size_t num_vco; #define SUPPORTS_OFFLINE_REQ BIT(0) -#define SUPPORTS_16BIT_ALPHA BIT(1) #define SUPPORTS_FSM_MODE BIT(2) u8 flags; |