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authorGeorgi Djakov <georgi.djakov@linaro.org>2017-12-05 17:46:58 +0200
committerStephen Boyd <sboyd@codeaurora.org>2018-01-02 10:00:24 -0800
commit0c6ab1b8f8940d4ddbfff7ddff080cbfb5f32b02 (patch)
tree86310ba2d4e2a574951dffa428e33ac87972fa84 /drivers/clk/qcom/Kconfig
parent4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323 (diff)
downloadlinux-0c6ab1b8f8940d4ddbfff7ddff080cbfb5f32b02.tar.bz2
clk: qcom: Add A53 PLL support
The CPUs on Qualcomm MSM8916-based platforms are clocked by two PLLs, a primary (A53) CPU PLL and a secondary fixed-rate GPLL0. These sources are connected to a mux and half-integer divider, which is feeding the CPU cores. This patch adds support for the primary CPU PLL which generates the higher range of frequencies above 1GHz. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Tested-by: Amit Kucheria <amit.kucheria@linaro.org> [sboyd@codeaurora.org: Move to devm provider registration, NUL terminate frequency table, made tristate/modular] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/qcom/Kconfig')
-rw-r--r--drivers/clk/qcom/Kconfig10
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 9f6c278deead..49db9fda6548 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -12,6 +12,16 @@ config COMMON_CLK_QCOM
select REGMAP_MMIO
select RESET_CONTROLLER
+config QCOM_A53PLL
+ tristate "MSM8916 A53 PLL"
+ depends on COMMON_CLK_QCOM
+ default ARCH_QCOM
+ help
+ Support for the A53 PLL on MSM8916 devices. It provides
+ the CPU with frequencies above 1GHz.
+ Say Y if you want to support higher CPU frequencies on MSM8916
+ devices.
+
config QCOM_CLK_RPM
tristate "RPM based Clock Controller"
depends on COMMON_CLK_QCOM && MFD_QCOM_RPM