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authorJames Hogan <james.hogan@imgtec.com>2014-11-14 15:32:09 +0000
committerMichael Turquette <mturquette@linaro.org>2014-11-17 11:13:52 -0800
commite6d5e7d90be92cee626d7ec16ca9b06f1eed710b (patch)
treeb1fa0b4d8e1ab37e13a4ac68611ff90300f31883 /drivers/clk/pxa
parent9a6cb70f40b0268297024949eb0a2689e3b7769b (diff)
downloadlinux-e6d5e7d90be92cee626d7ec16ca9b06f1eed710b.tar.bz2
clk-divider: Fix READ_ONLY when divider > 1
Commit 79c6ab509558 (clk: divider: add CLK_DIVIDER_READ_ONLY flag) in v3.16 introduced the CLK_DIVIDER_READ_ONLY flag which caused the recalc_rate() and round_rate() clock callbacks to be omitted. However using this flag has the unfortunate side effect of causing the clock recalculation code when a clock rate change is attempted to always treat it as a pass-through clock, i.e. with a fixed divide of 1, which may not be the case. Child clock rates are then recalculated using the wrong parent rate. Therefore instead of dropping the recalc_rate() and round_rate() callbacks, alter clk_divider_bestdiv() to always report the current divider as the best divider so that it is never altered. For me the read only clock was the system clock, which divided the PLL rate by 2, from which both the UART and the SPI clocks were divided. Initial setting of the UART rate set it correctly, but when the SPI clock was set, the other child clocks were miscalculated. The UART clock was recalculated using the PLL rate as the parent rate, resulting in a UART new_rate of double what it should be, and a UART which spewed forth garbage when the rate changes were propagated. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Thomas Abraham <thomas.ab@samsung.com> Cc: Tomasz Figa <t.figa@samsung.com> Cc: Max Schwarz <max.schwarz@online.de> Cc: <stable@vger.kernel.org> # v3.16+ Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk/pxa')
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