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authorEzequiel Garcia <ezequiel.garcia@imgtec.com>2015-05-26 19:01:08 -0300
committerStephen Boyd <sboyd@codeaurora.org>2015-06-04 12:43:33 -0700
commite0b7a79524771ad368abefbbcbd73f130f8e500e (patch)
tree2cdb12e5ed2950199cd755ebfa5d36283eaaf0a2 /drivers/clk/pistachio
parent4f4adfbf8e655914bb80daa0252c90b62fd27d78 (diff)
downloadlinux-e0b7a79524771ad368abefbbcbd73f130f8e500e.tar.bz2
clk: pistachio: Lock the PLL when enabled upon rate change
Currently, when the rate is changed, the driver makes sure the PLL is enabled before doing so. This is done because the PLL cannot be locked while disabled. Once locked, the drivers returns the PLL to its previous enable/disable state. This is a bit cumbersome, and can be simplified. This commit reworks the .set_rate() functions for the integer and fractional PLLs. Upon rate change, the PLL is now locked only if it's already enabled. Also, the driver locks the PLL on .enable(). This makes sure the PLL is locked when enabled, and not locked when disabled. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/pistachio')
-rw-r--r--drivers/clk/pistachio/clk-pll.c28
1 files changed, 10 insertions, 18 deletions
diff --git a/drivers/clk/pistachio/clk-pll.c b/drivers/clk/pistachio/clk-pll.c
index 9ce1be779c9c..f12d5207e478 100644
--- a/drivers/clk/pistachio/clk-pll.c
+++ b/drivers/clk/pistachio/clk-pll.c
@@ -130,6 +130,8 @@ static int pll_gf40lp_frac_enable(struct clk_hw *hw)
val &= ~PLL_FRAC_CTRL4_BYPASS;
pll_writel(pll, val, PLL_CTRL4);
+ pll_lock(pll);
+
return 0;
}
@@ -155,17 +157,13 @@ static int pll_gf40lp_frac_set_rate(struct clk_hw *hw, unsigned long rate,
{
struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
struct pistachio_pll_rate_table *params;
- bool was_enabled;
+ int enabled = pll_gf40lp_frac_is_enabled(hw);
u32 val;
params = pll_get_params(pll, parent_rate, rate);
if (!params)
return -EINVAL;
- was_enabled = pll_gf40lp_frac_is_enabled(hw);
- if (!was_enabled)
- pll_gf40lp_frac_enable(hw);
-
val = pll_readl(pll, PLL_CTRL1);
val &= ~((PLL_CTRL1_REFDIV_MASK << PLL_CTRL1_REFDIV_SHIFT) |
(PLL_CTRL1_FBDIV_MASK << PLL_CTRL1_FBDIV_SHIFT));
@@ -184,10 +182,8 @@ static int pll_gf40lp_frac_set_rate(struct clk_hw *hw, unsigned long rate,
(params->postdiv2 << PLL_FRAC_CTRL2_POSTDIV2_SHIFT);
pll_writel(pll, val, PLL_CTRL2);
- pll_lock(pll);
-
- if (!was_enabled)
- pll_gf40lp_frac_disable(hw);
+ if (enabled)
+ pll_lock(pll);
return 0;
}
@@ -246,6 +242,8 @@ static int pll_gf40lp_laint_enable(struct clk_hw *hw)
val &= ~PLL_INT_CTRL2_BYPASS;
pll_writel(pll, val, PLL_CTRL2);
+ pll_lock(pll);
+
return 0;
}
@@ -271,17 +269,13 @@ static int pll_gf40lp_laint_set_rate(struct clk_hw *hw, unsigned long rate,
{
struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
struct pistachio_pll_rate_table *params;
- bool was_enabled;
+ int enabled = pll_gf40lp_laint_is_enabled(hw);
u32 val;
params = pll_get_params(pll, parent_rate, rate);
if (!params)
return -EINVAL;
- was_enabled = pll_gf40lp_laint_is_enabled(hw);
- if (!was_enabled)
- pll_gf40lp_laint_enable(hw);
-
val = pll_readl(pll, PLL_CTRL1);
val &= ~((PLL_CTRL1_REFDIV_MASK << PLL_CTRL1_REFDIV_SHIFT) |
(PLL_CTRL1_FBDIV_MASK << PLL_CTRL1_FBDIV_SHIFT) |
@@ -293,10 +287,8 @@ static int pll_gf40lp_laint_set_rate(struct clk_hw *hw, unsigned long rate,
(params->postdiv2 << PLL_INT_CTRL1_POSTDIV2_SHIFT);
pll_writel(pll, val, PLL_CTRL1);
- pll_lock(pll);
-
- if (!was_enabled)
- pll_gf40lp_laint_disable(hw);
+ if (enabled)
+ pll_lock(pll);
return 0;
}