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authorChao Xie <chao.xie@marvell.com>2014-10-31 10:13:42 +0800
committerMichael Turquette <mturquette@linaro.org>2014-11-12 16:33:37 -0800
commit61256133919e76ea51e458c9713a9ee9d9ec4a67 (patch)
tree5b6b31808520277a486cd68b039eba2eb0ac85aa /drivers/clk/mmp/clk-pxa168.c
parent2bd1e256e45052f2244403f822fd85aa64a6aa00 (diff)
downloadlinux-61256133919e76ea51e458c9713a9ee9d9ec4a67.tar.bz2
clk: mmp: add spin lock for clk-frac
The register used by clk-frac may be shared with other clocks. So it needs to use spin lock to protect the register access. Signed-off-by: Chao Xie <chao.xie@marvell.com> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk/mmp/clk-pxa168.c')
-rw-r--r--drivers/clk/mmp/clk-pxa168.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/mmp/clk-pxa168.c b/drivers/clk/mmp/clk-pxa168.c
index 75266ac80829..93e967c0f972 100644
--- a/drivers/clk/mmp/clk-pxa168.c
+++ b/drivers/clk/mmp/clk-pxa168.c
@@ -158,7 +158,7 @@ void __init pxa168_clk_init(void)
uart_pll = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
mpmu_base + MPMU_UART_PLL,
&uart_factor_masks, uart_factor_tbl,
- ARRAY_SIZE(uart_factor_tbl));
+ ARRAY_SIZE(uart_factor_tbl), &clk_lock);
clk_set_rate(uart_pll, 14745600);
clk_register_clkdev(uart_pll, "uart_pll", NULL);