diff options
| author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2017-04-01 15:02:25 +0200 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2017-04-07 17:45:30 +0200 |
| commit | b609338b26f5653aa211fc7af83477e2df6e3f0b (patch) | |
| tree | 78dda6ea81fead69b83a6f39e5899f25f03b89ee /drivers/clk/meson | |
| parent | 88e4ac68ea9a09e105c86070ebfa01ca482ca4c2 (diff) | |
| download | linux-b609338b26f5653aa211fc7af83477e2df6e3f0b.tar.bz2 | |
clk: meson: mpll: use 64bit math in rate_from_params
On Meson8b the MPLL parent clock (fixed_pll) has a rate of 2550MHz.
Multiplying this with SDM_DEN results in a value greater than 32bits.
This is not a problem on the 64bit Meson GX SoCs, but it may result in
undefined behavior on the older 32bit Meson8b SoC.
While rate_from_params was only introduced recently to make the math
reusable from _round_rate and _recalc_rate the original bug exists much
longer.
Fixes: 1c50da4f27 ("clk: meson: add mpll support")
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
[as discussed on the ml, use DIV_ROUND_UP_ULL]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'drivers/clk/meson')
| -rw-r--r-- | drivers/clk/meson/clk-mpll.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/meson/clk-mpll.c b/drivers/clk/meson/clk-mpll.c index d9462b505dcc..39eab69fe51a 100644 --- a/drivers/clk/meson/clk-mpll.c +++ b/drivers/clk/meson/clk-mpll.c @@ -79,7 +79,7 @@ static long rate_from_params(unsigned long parent_rate, if (n2 < N2_MIN) return -EINVAL; - return (parent_rate * SDM_DEN) / divisor; + return DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, divisor); } static void params_from_rate(unsigned long requested_rate, |