diff options
| author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2017-01-19 15:58:20 +0100 |
|---|---|---|
| committer | Kevin Hilman <khilman@baylibre.com> | 2017-01-23 10:18:21 -0800 |
| commit | 33d0fcdfe0e87070d96c678e554d711ae15b9fa6 (patch) | |
| tree | 572705e9afdd982329b78e7c592fdc949ddbf3e5 /drivers/clk/meson/gxbb.h | |
| parent | 0264a88d6153e6cd5ee61239058b2002f36dde6b (diff) | |
| download | linux-33d0fcdfe0e87070d96c678e554d711ae15b9fa6.tar.bz2 | |
clk: gxbb: add the SAR ADC clocks and expose them
The HHI_SAR_CLK_CNTL contains three SAR ADC specific clocks:
- a mux clock to choose between different ADC reference clocks (this is
2-bit wide, but the datasheet only lists the parents for the first
bit)
- a divider for the input/reference clock
- a gate which enables the ADC clock
Additionally this exposes the ADC core clock (CLKID_SAR_ADC) and
CLKID_SANA (which seems to enable the analog inputs, but unfortunately
there is no documentation for this - we just mimic what the vendor
driver does).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Diffstat (limited to 'drivers/clk/meson/gxbb.h')
| -rw-r--r-- | drivers/clk/meson/gxbb.h | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h index 2139e97f5e39..dc487180f847 100644 --- a/drivers/clk/meson/gxbb.h +++ b/drivers/clk/meson/gxbb.h @@ -191,7 +191,7 @@ #define CLKID_PERIPHS 20 #define CLKID_SPICC 21 /* CLKID_I2C */ -#define CLKID_SAR_ADC 23 +/* #define CLKID_SAR_ADC */ #define CLKID_SMART_CARD 24 #define CLKID_RNG0 25 #define CLKID_UART0 26 @@ -237,7 +237,7 @@ #define CLKID_MMC_PCLK 66 #define CLKID_DVIN 67 #define CLKID_UART2 68 -#define CLKID_SANA 69 +/* #define CLKID_SANA */ #define CLKID_VPU_INTR 70 #define CLKID_SEC_AHB_AHB3_BRIDGE 71 #define CLKID_CLK81_A53 72 @@ -265,8 +265,11 @@ /* CLKID_SD_EMMC_A */ /* CLKID_SD_EMMC_B */ /* CLKID_SD_EMMC_C */ +/* CLKID_SAR_ADC_CLK */ +/* CLKID_SAR_ADC_SEL */ +#define CLKID_SAR_ADC_DIV 99 -#define NR_CLKS 97 +#define NR_CLKS 100 /* include the CLKIDs that have been made part of the stable DT binding */ #include <dt-bindings/clock/gxbb-clkc.h> |