diff options
| author | Jerome Brunet <jbrunet@baylibre.com> | 2018-02-19 12:21:45 +0100 |
|---|---|---|
| committer | Neil Armstrong <narmstrong@baylibre.com> | 2018-03-13 10:09:58 +0100 |
| commit | 05f814402d6174369b3b29832cbb5eb5ed287059 (patch) | |
| tree | 55806276dd6ea4734e2ec86238680c4e4ec06961 /drivers/clk/meson/axg.h | |
| parent | 513b67ac39b0ef91761d94d1d6e31bb84e380744 (diff) | |
| download | linux-05f814402d6174369b3b29832cbb5eb5ed287059.tar.bz2 | |
clk: meson: add fdiv clock gates
Fdiv fixed dividers clocks of the fixed_pll can actually gate
independently. We never had an issue so far because these clocks
were provided 'enabled' by the bootloader.
Add these gates to enable/disable the clocks when required.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Diffstat (limited to 'drivers/clk/meson/axg.h')
| -rw-r--r-- | drivers/clk/meson/axg.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/clk/meson/axg.h b/drivers/clk/meson/axg.h index 6e5dc65041b5..b421df6a7ea0 100644 --- a/drivers/clk/meson/axg.h +++ b/drivers/clk/meson/axg.h @@ -122,8 +122,13 @@ #define CLKID_MPLL2_DIV 67 #define CLKID_MPLL3_DIV 68 #define CLKID_MPLL_PREDIV 70 +#define CLKID_FCLK_DIV2_DIV 71 +#define CLKID_FCLK_DIV3_DIV 72 +#define CLKID_FCLK_DIV4_DIV 73 +#define CLKID_FCLK_DIV5_DIV 74 +#define CLKID_FCLK_DIV7_DIV 75 -#define NR_CLKS 71 +#define NR_CLKS 76 /* include the CLKIDs that have been made part of the DT binding */ #include <dt-bindings/clock/axg-clkc.h> |