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| author | Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com> | 2017-07-09 20:40:05 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-07-17 11:51:00 -0700 |
| commit | 3a11c6618e176aecf129c6d2f0cbc9440672f378 (patch) | |
| tree | 7714295489241cfd13ddb0ba856ab2be9e83c79f /drivers/clk/mediatek | |
| parent | b191155541f2a4cfbe62697c8d65919549f948c0 (diff) | |
| download | linux-3a11c6618e176aecf129c6d2f0cbc9440672f378.tar.bz2 | |
dt: Add bindings for IDT VersaClock 5P49V5925
IDT VersaClock 5 5P49V5925 has 5 clock outputs, 4 fractional dividers.
Input clock source can be taken only from external reference clock.
Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/mediatek')
0 files changed, 0 insertions, 0 deletions