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authorPaul Cercueil <paul@crapouillou.net>2018-05-20 16:31:14 +0000
committerStephen Boyd <sboyd@kernel.org>2018-06-01 23:21:32 -0700
commit11b689a3e790791ceeb17e3fe25046ad56ac966d (patch)
tree953e3957991bcf06e822e39f74b9642c702f3933 /drivers/clk/ingenic
parent261a831f042c906412099e8a4f73d954cb5370b4 (diff)
downloadlinux-11b689a3e790791ceeb17e3fe25046ad56ac966d.tar.bz2
clk: ingenic: jz4770: Change OTG from custom to standard gated clock
We now have the means to express the specificities of the OTG clock with the common CGU code. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/ingenic')
-rw-r--r--drivers/clk/ingenic/jz4770-cgu.c42
1 files changed, 5 insertions, 37 deletions
diff --git a/drivers/clk/ingenic/jz4770-cgu.c b/drivers/clk/ingenic/jz4770-cgu.c
index c78d369b9403..226c8016f6b0 100644
--- a/drivers/clk/ingenic/jz4770-cgu.c
+++ b/drivers/clk/ingenic/jz4770-cgu.c
@@ -42,7 +42,6 @@
/* bits within the OPCR register */
#define OPCR_SPENDH BIT(5) /* UHC PHY suspend */
-#define OPCR_SPENDN BIT(7) /* OTG PHY suspend */
/* bits within the USBPCR1 register */
#define USBPCR1_UHC_POWER BIT(5) /* UHC PHY power down */
@@ -83,37 +82,6 @@ static const struct clk_ops jz4770_uhc_phy_ops = {
.is_enabled = jz4770_uhc_phy_is_enabled,
};
-static int jz4770_otg_phy_enable(struct clk_hw *hw)
-{
- void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
-
- writel(readl(reg_opcr) | OPCR_SPENDN, reg_opcr);
-
- /* Wait for the clock to be stable */
- udelay(50);
- return 0;
-}
-
-static void jz4770_otg_phy_disable(struct clk_hw *hw)
-{
- void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
-
- writel(readl(reg_opcr) & ~OPCR_SPENDN, reg_opcr);
-}
-
-static int jz4770_otg_phy_is_enabled(struct clk_hw *hw)
-{
- void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
-
- return !!(readl(reg_opcr) & OPCR_SPENDN);
-}
-
-static const struct clk_ops jz4770_otg_phy_ops = {
- .enable = jz4770_otg_phy_enable,
- .disable = jz4770_otg_phy_disable,
- .is_enabled = jz4770_otg_phy_is_enabled,
-};
-
static const s8 pll_od_encoding[8] = {
0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3,
};
@@ -410,6 +378,11 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
.parents = { JZ4770_CLK_MMC2_MUX, },
.gate = { CGU_REG_CLKGR0, 12 },
},
+ [JZ4770_CLK_OTG_PHY] = {
+ "usb_phy", CGU_CLK_GATE,
+ .parents = { JZ4770_CLK_OTG },
+ .gate = { CGU_REG_OPCR, 7, true, 50 },
+ },
/* Custom clocks */
@@ -418,11 +391,6 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
.parents = { JZ4770_CLK_UHC, -1, -1, -1 },
.custom = { &jz4770_uhc_phy_ops },
},
- [JZ4770_CLK_OTG_PHY] = {
- "usb_phy", CGU_CLK_CUSTOM,
- .parents = { JZ4770_CLK_OTG, -1, -1, -1 },
- .custom = { &jz4770_otg_phy_ops },
- },
[JZ4770_CLK_EXT512] = {
"ext/512", CGU_CLK_FIXDIV,