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authorMarc Gonzalez <marc_gonzalez@sigmadesigns.com>2015-10-30 13:25:28 +0100
committerStephen Boyd <sboyd@codeaurora.org>2015-11-16 11:07:06 -0800
commited12dfc92f01690af65701dbc2839df3524980d3 (patch)
tree3bc3fd6637b587ce5d1562a41df0d83145eeac10 /drivers/clk/clk-tango4.c
parenta085f877a882b465fce74188c9d8efd12bd5acd4 (diff)
downloadlinux-ed12dfc92f01690af65701dbc2839df3524980d3.tar.bz2
clk: tango4: clkgen driver for Tango4 platforms
Provide support for Sigma Designs Tango4 clock generator. NOTE: This driver is incompatible with Tango3 clkgen. Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com> [sboyd@codeaurora.org: Add kernel.h include for panic/sprintf] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/clk-tango4.c')
-rw-r--r--drivers/clk/clk-tango4.c61
1 files changed, 61 insertions, 0 deletions
diff --git a/drivers/clk/clk-tango4.c b/drivers/clk/clk-tango4.c
new file mode 100644
index 000000000000..004ab7dfcfe3
--- /dev/null
+++ b/drivers/clk/clk-tango4.c
@@ -0,0 +1,61 @@
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
+#include <linux/init.h>
+#include <linux/io.h>
+
+static struct clk *out[2];
+static struct clk_onecell_data clk_data = { out, 2 };
+
+#define SYSCLK_CTRL 0x20
+#define CPUCLK_CTRL 0x24
+#define LEGACY_DIV 0x3c
+
+#define PLL_N(val) (((val) >> 0) & 0x7f)
+#define PLL_K(val) (((val) >> 13) & 0x7)
+#define PLL_M(val) (((val) >> 16) & 0x7)
+#define DIV_INDEX(val) (((val) >> 8) & 0xf)
+
+static void __init make_pll(int idx, const char *parent, void __iomem *base)
+{
+ char name[8];
+ u32 val, mul, div;
+
+ sprintf(name, "pll%d", idx);
+ val = readl_relaxed(base + idx*8);
+ mul = PLL_N(val) + 1;
+ div = (PLL_M(val) + 1) << PLL_K(val);
+ clk_register_fixed_factor(NULL, name, parent, 0, mul, div);
+}
+
+static int __init get_div(void __iomem *base)
+{
+ u8 sysclk_tab[16] = { 2, 4, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4 };
+ int idx = DIV_INDEX(readl_relaxed(base + LEGACY_DIV));
+
+ return sysclk_tab[idx];
+}
+
+static void __init tango4_clkgen_setup(struct device_node *np)
+{
+ int div, ret;
+ void __iomem *base = of_iomap(np, 0);
+ const char *parent = of_clk_get_parent_name(np, 0);
+
+ if (!base)
+ panic("%s: invalid address\n", np->full_name);
+
+ make_pll(0, parent, base);
+ make_pll(1, parent, base);
+
+ out[0] = clk_register_divider(NULL, "cpuclk", "pll0", 0,
+ base + CPUCLK_CTRL, 8, 8, CLK_DIVIDER_ONE_BASED, NULL);
+
+ div = readl_relaxed(base + SYSCLK_CTRL) & BIT(23) ? get_div(base) : 4;
+ out[1] = clk_register_fixed_factor(NULL, "sysclk", "pll1", 0, 1, div);
+
+ ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+ if (IS_ERR(out[0]) || IS_ERR(out[1]) || ret < 0)
+ panic("%s: clk registration failed\n", np->full_name);
+}
+CLK_OF_DECLARE(tango4_clkgen, "sigma,tango4-clkgen", tango4_clkgen_setup);