diff options
author | Linus Walleij <linus.walleij@linaro.org> | 2013-04-16 21:38:29 +0200 |
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committer | Linus Walleij <linus.walleij@linaro.org> | 2013-05-12 21:49:56 +0200 |
commit | 6e2b07a172b6ed98c7cdc301333b2d9f86c11880 (patch) | |
tree | dcc6d0272e2f168364b0a5ec69f0ff8f4fabbd9e /drivers/clk/clk-nomadik.c | |
parent | c7785ea0d279322bf92107d9a4fee195f5148c08 (diff) | |
download | linux-6e2b07a172b6ed98c7cdc301333b2d9f86c11880.tar.bz2 |
ARM: nomadik: convert all clocks except timer to dt
This moves all Nomadik clocks except the one used for the
timer/clocksource over to the device tree.
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/clk/clk-nomadik.c')
-rw-r--r-- | drivers/clk/clk-nomadik.c | 26 |
1 files changed, 7 insertions, 19 deletions
diff --git a/drivers/clk/clk-nomadik.c b/drivers/clk/clk-nomadik.c index 6b4c70f7d23d..19f197ccf28d 100644 --- a/drivers/clk/clk-nomadik.c +++ b/drivers/clk/clk-nomadik.c @@ -3,24 +3,24 @@ #include <linux/err.h> #include <linux/io.h> #include <linux/clk-provider.h> +#include <linux/of.h> /* * The Nomadik clock tree is described in the STN8815A12 DB V4.2 * reference manual for the chip, page 94 ff. */ +static const __initconst struct of_device_id cpu8815_clk_match[] = { + { .compatible = "fixed-clock", .data = of_fixed_clk_setup, }, + { /* sentinel */ } +}; + void __init nomadik_clk_init(void) { struct clk *clk; clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0); clk_register_clkdev(clk, "apb_pclk", NULL); - clk_register_clkdev(clk, NULL, "gpio.0"); - clk_register_clkdev(clk, NULL, "gpio.1"); - clk_register_clkdev(clk, NULL, "gpio.2"); - clk_register_clkdev(clk, NULL, "gpio.3"); - clk_register_clkdev(clk, NULL, "rng"); - clk_register_clkdev(clk, NULL, "fsmc-nand"); /* * The 2.4 MHz TIMCLK reference clock is active at boot time, this is @@ -32,17 +32,5 @@ void __init nomadik_clk_init(void) clk_register_clkdev(clk, NULL, "mtu0"); clk_register_clkdev(clk, NULL, "mtu1"); - /* - * At boot time, PLL2 is set to generate a set of fixed clocks, - * one of them is CLK48, the 48 MHz clock, routed to the UART, MMC/SD - * I2C, IrDA, USB and SSP blocks. - */ - clk = clk_register_fixed_rate(NULL, "CLK48", NULL, CLK_IS_ROOT, - 48000000); - clk_register_clkdev(clk, NULL, "uart0"); - clk_register_clkdev(clk, NULL, "uart1"); - clk_register_clkdev(clk, NULL, "mmci"); - clk_register_clkdev(clk, NULL, "ssp"); - clk_register_clkdev(clk, NULL, "nmk-i2c.0"); - clk_register_clkdev(clk, NULL, "nmk-i2c.1"); + of_clk_init(cpu8815_clk_match); } |