diff options
| author | Gerhard Sittig <gsi@denx.de> | 2013-07-22 14:14:40 +0200 |
|---|---|---|
| committer | Mike Turquette <mturquette@linaro.org> | 2013-08-27 17:50:38 -0700 |
| commit | aa514ce34b65e3dc01f95a0b470b39bbb7e09998 (patch) | |
| tree | 6d83d3f8e7560e5cd46fafe39960cd78cdfdc815 /drivers/clk/clk-mux.c | |
| parent | 29f79cb713c5173457b80602adab357403f22c48 (diff) | |
| download | linux-aa514ce34b65e3dc01f95a0b470b39bbb7e09998.tar.bz2 | |
clk: wrap I/O access for improved portability
the common clock drivers were motivated/initiated by ARM development
and apparently assume little endian peripherals
wrap register/peripherals access in the common code (div, gate, mux)
in preparation of adding COMMON_CLK support for other platforms
Signed-off-by: Gerhard Sittig <gsi@denx.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk/clk-mux.c')
| -rw-r--r-- | drivers/clk/clk-mux.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index 0811633fcc4d..4f96ff3ba728 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -42,7 +42,7 @@ static u8 clk_mux_get_parent(struct clk_hw *hw) * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so * val = 0x4 really means "bit 2, index starts at bit 0" */ - val = readl(mux->reg) >> mux->shift; + val = clk_readl(mux->reg) >> mux->shift; val &= mux->mask; if (mux->table) { @@ -89,11 +89,11 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index) if (mux->flags & CLK_MUX_HIWORD_MASK) { val = mux->mask << (mux->shift + 16); } else { - val = readl(mux->reg); + val = clk_readl(mux->reg); val &= ~(mux->mask << mux->shift); } val |= index << mux->shift; - writel(val, mux->reg); + clk_writel(val, mux->reg); if (mux->lock) spin_unlock_irqrestore(mux->lock, flags); |