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authorHarvey Hunt <harvey.hunt@imgtec.com>2016-05-09 17:29:52 +0100
committerStephen Boyd <sboyd@codeaurora.org>2016-05-12 14:48:25 -0700
commit4afe2d1a6ed5cba794aeeaa816e7c97a45167b01 (patch)
treee88fd50b5e791760c7abb20f01e087c53583fe34 /drivers/clk/clk-fixed-rate.c
parent5707291c6cada6db7344c90a548d02f427bf376c (diff)
downloadlinux-4afe2d1a6ed5cba794aeeaa816e7c97a45167b01.tar.bz2
clk: ingenic: Allow divider value to be divided
The JZ4780's MSC clock divider registers multiply the clock divider by 2. This means that MMC devices run at half their expected speed. Add the ability to divide the clock divider in order to solve this. Signed-off-by: Harvey Hunt <harvey.hunt@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/clk-fixed-rate.c')
0 files changed, 0 insertions, 0 deletions