diff options
| author | David Woodhouse <David.Woodhouse@intel.com> | 2009-07-29 10:25:58 +0100 |
|---|---|---|
| committer | David Woodhouse <David.Woodhouse@intel.com> | 2009-08-03 09:05:00 +0100 |
| commit | 6a12235c7d2d75c7d94b9afcaaecd422ff845ce0 (patch) | |
| tree | 416ec7de6c42fa5dd7885b53388a1bbee0b3aeed /drivers/char/agp/intel-agp.c | |
| parent | f692775d7e0a22477143cd884e45c955448ac7d2 (diff) | |
| download | linux-6a12235c7d2d75c7d94b9afcaaecd422ff845ce0.tar.bz2 | |
agp: kill phys_to_gart() and gart_to_phys()
There seems to be no reason for these -- they're a 1:1 mapping on all
platforms.
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'drivers/char/agp/intel-agp.c')
| -rw-r--r-- | drivers/char/agp/intel-agp.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c index d8c80d8be5e2..aa8889e8afc8 100644 --- a/drivers/char/agp/intel-agp.c +++ b/drivers/char/agp/intel-agp.c @@ -288,7 +288,7 @@ static void intel_agp_insert_sg_entries(struct agp_memory *mem, for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { writel(agp_bridge->driver->mask_memory(agp_bridge, - phys_to_gart(page_to_phys(mem->pages[i])), mask_type), + page_to_phys(mem->pages[i]), mask_type), intel_private.gtt+j); } @@ -470,8 +470,7 @@ static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start, global_cache_flush(); for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { writel(agp_bridge->driver->mask_memory(agp_bridge, - phys_to_gart(page_to_phys(mem->pages[i])), - mask_type), + page_to_phys(mem->pages[i]), mask_type), intel_private.registers+I810_PTE_BASE+(j*4)); } readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); @@ -977,7 +976,7 @@ static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start, for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { writel(agp_bridge->driver->mask_memory(agp_bridge, - phys_to_gart(page_to_phys(mem->pages[i])), mask_type), + page_to_phys(mem->pages[i]), mask_type), intel_private.registers+I810_PTE_BASE+(j*4)); } readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); |