diff options
| author | Alan Cox <alan@lxorguk.ukuu.org.uk> | 2007-07-24 15:17:48 +0100 |
|---|---|---|
| committer | Jeff Garzik <jeff@garzik.org> | 2007-07-24 16:55:02 -0400 |
| commit | 64a8170975947978ea4094dd6c4b1f41119d6ae6 (patch) | |
| tree | 5bceaf47ad8b34f71e189ceac0095235c3347f5d /drivers/ata/pata_hpt37x.c | |
| parent | 5c8d52015c09b42632a73896f8a80cff64c5c1d1 (diff) | |
| download | linux-64a8170975947978ea4094dd6c4b1f41119d6ae6.tar.bz2 | |
pata_hpt37x: Fix 2.6.22 clock PLL regression
Just one version of Linux ago
The PLL code broke - oh no!
But set the right mode
And fix up the code
Makes the PLL timing sync go
[whatever happened to the sailor from Nantucket, hero of many limericks? -jg]
Closes-bug: #8791
Signed-off-by: Alan Cox <alan@redhat.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/ata/pata_hpt37x.c')
| -rw-r--r-- | drivers/ata/pata_hpt37x.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/ata/pata_hpt37x.c b/drivers/ata/pata_hpt37x.c index b0af65aadde3..84d9c5568567 100644 --- a/drivers/ata/pata_hpt37x.c +++ b/drivers/ata/pata_hpt37x.c @@ -26,7 +26,7 @@ #include <linux/libata.h> #define DRV_NAME "pata_hpt37x" -#define DRV_VERSION "0.6.6" +#define DRV_VERSION "0.6.7" struct hpt_clock { u8 xfer_speed; @@ -1103,17 +1103,17 @@ static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id) /* Select the DPLL clock. */ pci_write_config_byte(dev, 0x5b, 0x21); - pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low); + pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100); for(adjust = 0; adjust < 8; adjust++) { if (hpt37x_calibrate_dpll(dev)) break; /* See if it'll settle at a fractionally different clock */ - if ((adjust & 3) == 3) { - f_low --; - f_high ++; - } - pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low); + if (adjust & 1) + f_low -= adjust >> 1; + else + f_high += adjust >> 1; + pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100); } if (adjust == 8) { printk(KERN_WARNING "hpt37x: DPLL did not stabilize.\n"); |