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authorJulia Lawall <Julia.Lawall@inria.fr>2022-03-18 11:37:16 +0100
committerArnd Bergmann <arnd@arndb.de>2022-03-19 22:33:59 +0100
commit339ac71b233ee9ab5036be3abca0e5df793b5f64 (patch)
tree359f30cb496c9a7793838798fd1e1136293cd752 /arch
parent8e145bc705e738ebe7ed6c53d93278981d9af356 (diff)
downloadlinux-339ac71b233ee9ab5036be3abca0e5df793b5f64.tar.bz2
ARM: spear: fix typos in comments
Various spelling mistakes in comments. Detected with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr> Link: https://lore.kernel.org/r/20220318103729.157574-21-Julia.Lawall@inria.fr' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-spear/spear13xx.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-spear/spear13xx.c b/arch/arm/mach-spear/spear13xx.c
index 74d1ca2a529a..b38391e9d8bf 100644
--- a/arch/arm/mach-spear/spear13xx.c
+++ b/arch/arm/mach-spear/spear13xx.c
@@ -29,7 +29,7 @@ void __init spear13xx_l2x0_init(void)
/*
* 512KB (64KB/way), 8-way associativity, parity supported
*
- * FIXME: 9th bit, of Auxillary Controller register must be set
+ * FIXME: 9th bit, of Auxiliary Controller register must be set
* for some spear13xx devices for stable L2 operation.
*
* Enable Early BRESP, L2 prefetch for Instruction and Data,