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| author | Peter Zijlstra <a.p.zijlstra@chello.nl> | 2011-11-14 10:03:25 +0100 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2011-11-14 13:03:44 +0100 |
| commit | ed13ec58bfe0d5dc95f748e6118432cb0fa283cb (patch) | |
| tree | 378bc886f4a59d7564fb8021a6392af62ba42ced /arch | |
| parent | aa2bc1ade59003a379ffc485d6da2d92ea3370a6 (diff) | |
| download | linux-ed13ec58bfe0d5dc95f748e6118432cb0fa283cb.tar.bz2 | |
perf/x86: Enable raw event access to Intel offcore events
Now that the core offcore support is fixed up (thanks Stephane) and we
have sane generic events utilizing them, re-enable the raw access to
the feature as well.
Note that it doesn't matter if you use event 0x1b7 or 0x1bb to specify
an offcore event, either one works and neither guarantees you'll end
up on a particular offcore MSR.
Based on original patch from: Vince Weaver <vweaver1@eecs.utk.edu>.
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Vince Weaver <vweaver1@eecs.utk.edu>.
Cc: Stephane Eranian <eranian@google.com>
Link: http://lkml.kernel.org/r/alpine.DEB.2.00.1108031200390.703@cl320.eecs.utk.edu
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/x86/kernel/cpu/perf_event.c | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c index ff0e8d498750..2bda212a0010 100644 --- a/arch/x86/kernel/cpu/perf_event.c +++ b/arch/x86/kernel/cpu/perf_event.c @@ -312,12 +312,8 @@ int x86_setup_perfctr(struct perf_event *event) return -EOPNOTSUPP; } - /* - * Do not allow config1 (extended registers) to propagate, - * there's no sane user-space generalization yet: - */ if (attr->type == PERF_TYPE_RAW) - return 0; + return x86_pmu_extra_regs(event->attr.config, event); if (attr->type == PERF_TYPE_HW_CACHE) return set_ext_hw_attr(hwc, event); |