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| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2011-08-27 00:37:38 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2011-08-28 10:39:54 +0100 |
| commit | f35235a315a167e38e8e5bc9e476dcd7c932612c (patch) | |
| tree | 71698ea7ffd658ccc4e9e65a1ea381ee7f63c539 /arch | |
| parent | 1c0270cd3a7a66148c3f72cab8fffc650d196d1d (diff) | |
| download | linux-f35235a315a167e38e8e5bc9e476dcd7c932612c.tar.bz2 | |
ARM: pm: some ARMv7 requires a dsb in resume to ensure correctness
Add a dsb after the isb to ensure that the previous writes to the
CP15 registers take effect before we enable the MMU.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mm/proc-v7.S | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index dec72ee9f7af..a773f4e2869c 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -255,6 +255,7 @@ ENTRY(cpu_v7_do_resume) mcr p15, 0, r4, c10, c2, 0 @ write PRRR mcr p15, 0, r5, c10, c2, 1 @ write NMRR isb + dsb mov r0, r9 @ control register mov r2, r7, lsr #14 @ get TTB0 base mov r2, r2, lsl #14 |