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| author | Len Brown <len.brown@intel.com> | 2017-01-11 23:17:24 -0500 |
|---|---|---|
| committer | Len Brown <len.brown@intel.com> | 2017-03-01 00:14:03 -0500 |
| commit | e651262477c6d8cba79dffc1a6039da43d9c96b0 (patch) | |
| tree | 75628064980e6094ef835f540196b01d64558d66 /arch | |
| parent | 710f273ba96182fd93ee8540ae06583c7d889d7c (diff) | |
| download | linux-e651262477c6d8cba79dffc1a6039da43d9c96b0.tar.bz2 | |
tools/power turbostat: further decode MSR_IA32_MISC_ENABLE
Decode MISC_ENABLE.NO_TURBO,
also use the #defines in msr-index.h for decoding this register
cpu0: MSR_IA32_MISC_ENABLE: 0x00850089 (TCC EIST MWAIT TURBO)
Although it is not architectural, decode also
MSR_IA32_MISC_ENABLE.prefetch-disable (bit-9).
documented to be present on: Core, P4, Intel-Xeon
reserved on: Atom, Silvermont, Nehalem, SNB, PHI ec.
Signed-off-by: Len Brown <len.brown@intel.com>
Diffstat (limited to 'arch')
0 files changed, 0 insertions, 0 deletions