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authorAndrzej Hajda <a.hajda@samsung.com>2017-01-23 11:05:49 +0100
committerKrzysztof Kozlowski <krzk@kernel.org>2017-01-23 18:32:57 +0200
commit4e09f4a6b620d6617f2ce7ee858c6d98176d156e (patch)
treeaa6ad3219a072c8581e961073dfd77f27461f0c0 /arch
parent9f6fe6f0137642d487a5add88fc205a7496e4f69 (diff)
downloadlinux-4e09f4a6b620d6617f2ce7ee858c6d98176d156e.tar.bz2
arm64: dts: exynos: configure TV path clocks for Ultra HD modes
Ultra HD modes requires clock ticking at increased rate. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi12
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
index a5c866901e93..13a0950b57e2 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
@@ -217,6 +217,18 @@
assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>;
};
+&cmu_disp {
+ assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
+ <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
+ assigned-clock-parents = <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
+ <0>,
+ <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
+ assigned-clock-rates = <0>, <400000000>;
+};
+
&cmu_fsys {
assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
<&cmu_top CLK_MOUT_SCLK_USBHOST30>,