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authorMasahiro Yamada <yamada.masahiro@socionext.com>2017-02-27 14:29:03 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2017-02-27 18:43:46 -0800
commit4e0385dd7469d933c4adf84a617f872ca547aa07 (patch)
tree92256b7941fc512dcd9c651b78199725261cc85a /arch
parent89d790ab31d033d67635f6362d57ea64e47708fa (diff)
downloadlinux-4e0385dd7469d933c4adf84a617f872ca547aa07.tar.bz2
scripts/spelling.txt: add "efective" pattern and fix typo instances
Fix typos and add the following to the scripts/spelling.txt: efective||effective While we are here, fix the "addres" as well in the touched line in arch/openrisc/kernel/entry.S. Link: http://lkml.kernel.org/r/1481573103-11329-10-git-send-email-yamada.masahiro@socionext.com Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/m68k/ifpsp060/src/isp.S2
-rw-r--r--arch/openrisc/kernel/entry.S2
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/m68k/ifpsp060/src/isp.S b/arch/m68k/ifpsp060/src/isp.S
index 6dccda766e22..b865c1a052ba 100644
--- a/arch/m68k/ifpsp060/src/isp.S
+++ b/arch/m68k/ifpsp060/src/isp.S
@@ -3814,7 +3814,7 @@ CAS2W2_FILLER:
# (3) Save current DFC/SFC (ASSUMED TO BE EQUAL!!!); Then set #
# SFC/DFC according to whether exception occurred in user or #
# supervisor mode. #
-# (4) Use "plpaw" instruction to pre-load ATC with efective #
+# (4) Use "plpaw" instruction to pre-load ATC with effective #
# address page(s). THIS SHOULD NOT FAULT!!! The relevant #
# page(s) should have been made resident prior to entering #
# this routine. #
diff --git a/arch/openrisc/kernel/entry.S b/arch/openrisc/kernel/entry.S
index 459e4b129e4f..1b7160c79646 100644
--- a/arch/openrisc/kernel/entry.S
+++ b/arch/openrisc/kernel/entry.S
@@ -332,7 +332,7 @@ EXCEPTION_ENTRY(_alignment_handler)
#if 0
EXCEPTION_ENTRY(_alignment_handler)
-// l.mfspr r2,r0,SPR_EEAR_BASE /* Load the efective addres */
+// l.mfspr r2,r0,SPR_EEAR_BASE /* Load the effective address */
l.addi r2,r4,0
// l.mfspr r5,r0,SPR_EPCR_BASE /* Load the insn address */
l.lwz r5,PT_PC(r1)