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authorTigran Tadevosyan <tigran.tadevosyan@arm.com>2019-04-05 14:16:13 +0100
committerRussell King <rmk+kernel@armlinux.org.uk>2019-04-23 17:28:37 +0100
commitc3143967807adb1357c36b68a7563fc0c4e1f615 (patch)
tree366d4c17a8d55bf9c4830fd67630c4f7b9dc7016 /arch
parent503621628b32782a07b2318e4112bd4372aa3401 (diff)
downloadlinux-c3143967807adb1357c36b68a7563fc0c4e1f615.tar.bz2
ARM: 8856/1: NOMMU: Fix CCR register faulty initialization when MPU is disabled
When CONFIG_ARM_MPU is not defined, the base address of v7M SCB register is not initialized with correct value. This prevents enabling I/D caches when the L1 cache poilcy is applied in kernel. Fixes: 3c24121039c9da14692eb48f6e39565b28c0f3cf ("ARM: 8756/1: NOMMU: Postpone MPU activation till __after_proc_init") Signed-off-by: Tigran Tadevosyan <tigran.tadevosyan@arm.com> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/kernel/head-nommu.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index c08d2d890f7b..b38bbd011b35 100644
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -133,9 +133,9 @@ __secondary_data:
*/
.text
__after_proc_init:
-#ifdef CONFIG_ARM_MPU
M_CLASS(movw r12, #:lower16:BASEADDR_V7M_SCB)
M_CLASS(movt r12, #:upper16:BASEADDR_V7M_SCB)
+#ifdef CONFIG_ARM_MPU
M_CLASS(ldr r3, [r12, 0x50])
AR_CLASS(mrc p15, 0, r3, c0, c1, 4) @ Read ID_MMFR0
and r3, r3, #(MMFR0_PMSA) @ PMSA field