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| author | Bjorn Helgaas <bhelgaas@google.com> | 2019-03-06 15:30:21 -0600 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2019-03-06 15:30:21 -0600 |
| commit | 7e5b22ddb2d400ace448483fa46323a6072ceca0 (patch) | |
| tree | bb4951baf2e84640f66511f358ec4bffd75c876e /arch | |
| parent | 2506419e06d4fda627376631e2619dec61b60968 (diff) | |
| parent | 85cef374d0ba93b8a2bd24850b97c1b34c666ccb (diff) | |
| download | linux-7e5b22ddb2d400ace448483fa46323a6072ceca0.tar.bz2 | |
Merge branch 'remotes/lorenzo/pci/endpoint'
- Use memcpy_fromio()/memcpy_toio() instead of plain memcpy() in PCI
endpoint framework (Wen Yang)
- Add interface to discover supported endpoint features to replace a
bitfield that wasn't flexible enough (Kishon Vijay Abraham I)
- Implement the new supported-feature interface for designware-plat,
dra7xx, rockchip, cadence (Kishon Vijay Abraham I)
- Fix issues with 64-bit BAR in endpoints (Kishon Vijay Abraham I)
- Add layerscape endpoint mode support (Xiaowei Bao)
* remotes/lorenzo/pci/endpoint:
misc: pci_endpoint_test: Add the layerscape EP device support
PCI: layerscape: Add EP mode support
arm64: dts: Add the PCIE EP node in dts
dt-bindings: add DT binding for the layerscape PCIe controller with EP mode
PCI: endpoint: Remove features member in struct pci_epc
PCI: designware-plat: Remove setting epc->features in Designware plat EP driver
PCI: rockchip: Remove pci_epf_linkup() from Rockchip EP driver
PCI: cadence: Remove pci_epf_linkup() from Cadence EP driver
PCI: pci-epf-test: Use pci_epc_get_features() to get EPC features
PCI: pci-epf-test: Do not allocate next BARs memory if current BAR is 64Bit
PCI: pci-epf-test: Remove setting epf_bar flags in function driver
PCI: endpoint: Fix pci_epf_alloc_space() to set correct MEM TYPE flags
PCI: endpoint: Add helper to get first unreserved BAR
PCI: cadence: Populate ->get_features() cdns_pcie_epc_ops
PCI: rockchip: Populate ->get_features() dw_pcie_ep_ops
PCI: pci-dra7xx: Populate ->get_features() dw_pcie_ep_ops
PCI: designware-plat: Populate ->get_features() dw_pcie_ep_ops
PCI: dwc: Add ->get_features() callback function to dw_pcie_ep_ops
PCI: endpoint: Add new pci_epc_ops to get EPC features
PCI: endpoint: functions: Use memcpy_fromio()/memcpy_toio()
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 34 |
1 files changed, 33 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 9a2106e60e19..576262e434a5 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -657,6 +657,17 @@ status = "disabled"; }; + pcie_ep@3400000 { + compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep"; + reg = <0x00 0x03400000 0x0 0x00100000 + 0x40 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ib-windows = <6>; + num-ob-windows = <8>; + num-lanes = <2>; + status = "disabled"; + }; + pcie@3500000 { compatible = "fsl,ls1046a-pcie"; reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ @@ -683,6 +694,17 @@ status = "disabled"; }; + pcie_ep@3500000 { + compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep"; + reg = <0x00 0x03500000 0x0 0x00100000 + 0x48 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ib-windows = <6>; + num-ob-windows = <8>; + num-lanes = <2>; + status = "disabled"; + }; + pcie@3600000 { compatible = "fsl,ls1046a-pcie"; reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ @@ -709,6 +731,17 @@ status = "disabled"; }; + pcie_ep@3600000 { + compatible = "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"; + reg = <0x00 0x03600000 0x0 0x00100000 + 0x50 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ib-windows = <6>; + num-ob-windows = <8>; + num-lanes = <2>; + status = "disabled"; + }; + qdma: dma-controller@8380000 { compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma"; reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ @@ -729,7 +762,6 @@ queue-sizes = <64 64>; big-endian; }; - }; reserved-memory { |