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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2013-10-04 09:03:51 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2013-10-04 09:03:51 -0700 |
| commit | 0bfdbf0e79ab20394c932f27f6d3a34b757035ef (patch) | |
| tree | e3876afb8842067a52dfccbb5a9393fd81db5ab5 /arch | |
| parent | 413df1cb434b9b73b517f78c231549add1ee1c99 (diff) | |
| parent | 5596b0b245fb9d2cefb5023b11061050351c1398 (diff) | |
| download | linux-0bfdbf0e79ab20394c932f27f6d3a34b757035ef.tar.bz2 | |
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS fixes from Ralf Baechle:
"Two small fixes for 3.12 only this week. I have a few more fixes
pending but those are conceptually more complex so will have to wait
for a bit longer"
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
MIPS: Fix forgotten preempt_enable() when CPU has inclusive pcaches
MIPS: Alchemy: MTX-1: fix incorrect placement of __initdata tag
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/mips/alchemy/board-mtx1.c | 2 | ||||
| -rw-r--r-- | arch/mips/mm/c-r4k.c | 2 |
2 files changed, 3 insertions, 1 deletions
diff --git a/arch/mips/alchemy/board-mtx1.c b/arch/mips/alchemy/board-mtx1.c index 4a9baa9f6330..9969dbab19e3 100644 --- a/arch/mips/alchemy/board-mtx1.c +++ b/arch/mips/alchemy/board-mtx1.c @@ -276,7 +276,7 @@ static struct platform_device mtx1_pci_host = { .resource = alchemy_pci_host_res, }; -static struct __initdata platform_device * mtx1_devs[] = { +static struct platform_device *mtx1_devs[] __initdata = { &mtx1_pci_host, &mtx1_gpio_leds, &mtx1_wdt, diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 627883bc6d5f..bc6f96fcb529 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -609,6 +609,7 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) r4k_blast_scache(); else blast_scache_range(addr, addr + size); + preempt_enable(); __sync(); return; } @@ -650,6 +651,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) */ blast_inv_scache_range(addr, addr + size); } + preempt_enable(); __sync(); return; } |