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| author | Helge Deller <deller@gmx.de> | 2022-05-07 15:31:16 +0200 |
|---|---|---|
| committer | Helge Deller <deller@gmx.de> | 2022-05-08 20:01:11 +0200 |
| commit | 9dc4241bb14afecd16518a0760bceb3d7359b12a (patch) | |
| tree | b439f7aba3b439dcde59a619b36be07e7b67c6cc /arch | |
| parent | 30c8e80f79329617012f07b09b70114592092ea4 (diff) | |
| download | linux-9dc4241bb14afecd16518a0760bceb3d7359b12a.tar.bz2 | |
Revert "parisc: Mark cr16 CPU clocksource unstable on all SMP machines"
This reverts commit afdb4a5b1d340e4afffc65daa21cc71890d7d589.
It triggers RCU stalls at boot with a 32-bit kernel.
Signed-off-by: Helge Deller <deller@gmx.de>
Noticed-by: John David Anglin <dave.anglin@bell.net>
Cc: stable@vger.kernel.org # v5.16+
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/parisc/kernel/time.c | 30 |
1 files changed, 22 insertions, 8 deletions
diff --git a/arch/parisc/kernel/time.c b/arch/parisc/kernel/time.c index bb27dfeeddfc..95ee9e1a364b 100644 --- a/arch/parisc/kernel/time.c +++ b/arch/parisc/kernel/time.c @@ -251,16 +251,30 @@ void __init time_init(void) static int __init init_cr16_clocksource(void) { /* - * The cr16 interval timers are not syncronized across CPUs, even if - * they share the same socket. + * The cr16 interval timers are not syncronized across CPUs on + * different sockets, so mark them unstable and lower rating on + * multi-socket SMP systems. */ if (num_online_cpus() > 1 && !running_on_qemu) { - /* mark sched_clock unstable */ - clear_sched_clock_stable(); - - clocksource_cr16.name = "cr16_unstable"; - clocksource_cr16.flags = CLOCK_SOURCE_UNSTABLE; - clocksource_cr16.rating = 0; + int cpu; + unsigned long cpu0_loc; + cpu0_loc = per_cpu(cpu_data, 0).cpu_loc; + + for_each_online_cpu(cpu) { + if (cpu == 0) + continue; + if ((cpu0_loc != 0) && + (cpu0_loc == per_cpu(cpu_data, cpu).cpu_loc)) + continue; + + /* mark sched_clock unstable */ + clear_sched_clock_stable(); + + clocksource_cr16.name = "cr16_unstable"; + clocksource_cr16.flags = CLOCK_SOURCE_UNSTABLE; + clocksource_cr16.rating = 0; + break; + } } /* register at clocksource framework */ |