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authorTirumalesh Chalamarla <tchalamarla@caviumnetworks.com>2016-02-04 10:45:25 -0800
committerMarc Zyngier <marc.zyngier@arm.com>2016-02-11 10:20:02 +0000
commit1a1ebd5fb1e203ee8cc73508cc7a38ac4b804596 (patch)
tree5a046e3c634ce678ac7c73e2293bc485024e8eb1 /arch
parent389a00d3ad02a06b5d6d692cce76fed6a3dae8b4 (diff)
downloadlinux-1a1ebd5fb1e203ee8cc73508cc7a38ac4b804596.tar.bz2
irqchip/gic-v3: Make sure read from ICC_IAR1_EL1 is visible on redestributor
The ARM GICv3 specification mentions the need for dsb after a read from the ICC_IAR1_EL1 register: 4.1.1 Physical CPU Interface: The effects of reading ICC_IAR0_EL1 and ICC_IAR1_EL1 on the state of a returned INTID are not guaranteed to be visible until after the execution of a DSB. Not having this could result in missed interrupts, so let's add the required barrier. [Marc: fixed commit message] Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Tirumalesh Chalamarla <tchalamarla@caviumnetworks.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm64/include/asm/arch_gicv3.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h
index 2731d3b25ed2..8ec88e5b290f 100644
--- a/arch/arm64/include/asm/arch_gicv3.h
+++ b/arch/arm64/include/asm/arch_gicv3.h
@@ -103,6 +103,7 @@ static inline u64 gic_read_iar_common(void)
u64 irqstat;
asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat));
+ dsb(sy);
return irqstat;
}