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authorAdam Buchbinder <adam.buchbinder@gmail.com>2016-02-23 15:28:52 -0800
committerJiri Kosina <jkosina@suse.cz>2016-04-18 12:45:53 +0200
commit0398b95fe4b3c90fbabfb39b77e635ec863ac040 (patch)
tree4e2e95cccfe64898ad945c74c0e6e828637a6416 /arch
parente0b1c817d85d1611b4f44f9c5b3e6426886206e0 (diff)
downloadlinux-0398b95fe4b3c90fbabfb39b77e635ec863ac040.tar.bz2
c6x: Fix misspellings in comments.
Signed-off-by: Adam Buchbinder <adam.buchbinder@gmail.com> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
Diffstat (limited to 'arch')
-rw-r--r--arch/c6x/include/asm/clock.h2
-rw-r--r--arch/c6x/platforms/cache.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/c6x/include/asm/clock.h b/arch/c6x/include/asm/clock.h
index bcf42b2b4b1e..e2f818a7a1d1 100644
--- a/arch/c6x/include/asm/clock.h
+++ b/arch/c6x/include/asm/clock.h
@@ -101,7 +101,7 @@ struct clk {
#define CLK_PLL BIT(2) /* PLL-derived clock */
#define PRE_PLL BIT(3) /* source is before PLL mult/div */
#define FIXED_DIV_PLL BIT(4) /* fixed divisor from PLL */
-#define FIXED_RATE_PLL BIT(5) /* fixed ouput rate PLL */
+#define FIXED_RATE_PLL BIT(5) /* fixed output rate PLL */
#define MAX_PLL_SYSCLKS 16
diff --git a/arch/c6x/platforms/cache.c b/arch/c6x/platforms/cache.c
index 46fd2d530271..ec3c887c79ec 100644
--- a/arch/c6x/platforms/cache.c
+++ b/arch/c6x/platforms/cache.c
@@ -145,7 +145,7 @@ loop:
spin_lock_irqsave(&cache_lock, flags);
/*
- * If another cache operation is occuring
+ * If another cache operation is occurring
*/
if (unlikely(imcr_get(wc_reg))) {
spin_unlock_irqrestore(&cache_lock, flags);