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authorManuel Lauss <manuel.lauss@gmail.com>2015-02-18 11:01:56 +0100
committerRalf Baechle <ralf@linux-mips.org>2015-02-20 13:01:42 +0100
commit69e4e63ec816a7e22cc3aa14bc7ef4ac734d370c (patch)
treee568482e3fd178211e3caa00f9cb4d64ae31a804 /arch
parent200276e6730c2817a77cfa6fc7e39ab3a63c4646 (diff)
downloadlinux-69e4e63ec816a7e22cc3aa14bc7ef4ac734d370c.tar.bz2
MIPS: Alchemy: Fix cpu clock calculation
The current code uses bits 0-6 of the sys_cpupll register to calculate core clock speed. However this is only valid on Au1300, on all earlier models the hardware only uses bits 0-5 to generate core clock. This fixes clock calculation on the MTX1 (Au1500), where bit 6 of cpupll is set as well, which ultimately lead the code to calculate a bogus cpu core clock and also uart base clock down the line. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Reported-by: John Crispin <blogic@openwrt.org> Tested-by: Bruno Randolf <br1@einfach.org> Cc: stable@vger.kernel.org [v3.17+] Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/9279/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/alchemy/common/clock.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/mips/alchemy/common/clock.c b/arch/mips/alchemy/common/clock.c
index 3612d76007a4..4b5ec49139c2 100644
--- a/arch/mips/alchemy/common/clock.c
+++ b/arch/mips/alchemy/common/clock.c
@@ -127,6 +127,8 @@ static unsigned long alchemy_clk_cpu_recalc(struct clk_hw *hw,
t = 396000000;
else {
t = alchemy_rdsys(AU1000_SYS_CPUPLL) & 0x7f;
+ if (alchemy_get_cputype() < ALCHEMY_CPU_AU1300)
+ t &= 0x3f;
t *= parent_rate;
}