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authorMatthew Leach <matthew.leach@arm.com>2012-09-11 17:56:57 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2012-09-16 00:16:16 +0100
commite1e5b7e4251c7538ca08c2c5545b0c2fbd8a6635 (patch)
tree3c98653fb149c9b8646922f6c7091d414e4a1b1d /arch
parent3f0c3c8fe30c725c1264fb6db8cc4b69db3a658a (diff)
downloadlinux-e1e5b7e4251c7538ca08c2c5545b0c2fbd8a6635.tar.bz2
ARM: 7532/1: decompressor: reset SCTLR.TRE for VMSA ARMv7 cores
This patch zeroes the SCTLR.TRE bit prior to setting the mapping as cacheable for ARMv7 cores in the decompressor, ensuring that the memory region attributes are obtained from the C and B bits, not from the page tables. Cc: Nicolas Pitre <nico@fluxnic.net> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Matthew Leach <matthew.leach@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Cc: <stable@vger.kernel.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boot/compressed/head.S1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 81769c1341fa..bc67cbff3944 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -653,6 +653,7 @@ __armv7_mmu_cache_on:
mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
#endif
mrc p15, 0, r0, c1, c0, 0 @ read control reg
+ bic r0, r0, #1 << 28 @ clear SCTLR.TRE
orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
orr r0, r0, #0x003c @ write buffer
#ifdef CONFIG_MMU