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| author | Ralf Baechle <ralf@linux-mips.org> | 2007-11-16 23:15:51 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2007-12-09 04:51:10 +0000 |
| commit | 5ef1b9a0f6cbb1269fc8b8d7704d146f22bf7aa6 (patch) | |
| tree | 134ed87dc69815f2f72d2a3b03b7b60f15218a6c /arch | |
| parent | 8f7e7d67cbcbcfd2c72d496f01f5e4c78853ef7d (diff) | |
| download | linux-5ef1b9a0f6cbb1269fc8b8d7704d146f22bf7aa6.tar.bz2 | |
[MIPS] Bigsur: Enable tickless and and highres timers.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/mips/configs/bigsur_defconfig | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig index 80b0c99c2cfb..3c70c9d16d01 100644 --- a/arch/mips/configs/bigsur_defconfig +++ b/arch/mips/configs/bigsur_defconfig @@ -76,9 +76,13 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y # CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set +CONFIG_CEVT_BCM1480=y +CONFIG_CSRC_BCM1480=y CONFIG_DMA_COHERENT=y CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set @@ -91,6 +95,11 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_CPU_LOONGSON2 is not set # CONFIG_CPU_MIPS32_R1 is not set # CONFIG_CPU_MIPS32_R2 is not set # CONFIG_CPU_MIPS64_R1 is not set |