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authorLennert Buytenhek <buytenh@wantstofly.org>2011-08-11 09:56:06 +0800
committerEric Miao <eric.y.miao@gmail.com>2011-08-11 10:10:26 +0800
commit392ba787bcc9b8d4786fb94949d270ec7414da55 (patch)
tree35bd233c9a35940b7dfe4e4f358992a33b7e9045 /arch
parent322a8b034003c0d46d39af85bf24fee27b902f48 (diff)
downloadlinux-392ba787bcc9b8d4786fb94949d270ec7414da55.tar.bz2
ARM: pxa: fix logic error in PJ4 iWMMXt handling
This got added in: commit ef6c84454f8567d4968c210d7d194fb711ed3739 Author: Haojian Zhuang <haojian.zhuang@marvell.com> Date: Wed Nov 24 11:54:25 2010 +0800 ARM: pxa: add iwmmx support for PJ4 which does: - mrc p15, 0, r2, c15, c1, 0 - orr r2, r2, #0x3 @ enable access to CP0 and CP1 - mcr p15, 0, r2, c15, c1, 0 + @ enable access to CP0 and CP1 + XSC(mrc p15, 0, r2, c15, c1, 0) + XSC(orr r2, r2, #0x3) + XSC(mcr p15, 0, r2, c15, c1, 0) but then later does: - mrc p15, 0, r4, c15, c1, 0 - orr r4, r4, #0x3 @ enable access to CP0 and CP1 - mcr p15, 0, r4, c15, c1, 0 + @ enable access to CP0 and CP1 + XSC(mrc p15, 0, r4, c15, c1, 0) + XSC(orr r4, r4, #0xf) + XSC(mcr p15, 0, r4, c15, c1, 0) Signed-off-by: Lennert Buytenhek <buytenh@laptop.org> Acked-by Haojian <haojian.zhuang@gmail.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/kernel/iwmmxt.S6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/kernel/iwmmxt.S b/arch/arm/kernel/iwmmxt.S
index 7fa3bb0d2397..a08783823b32 100644
--- a/arch/arm/kernel/iwmmxt.S
+++ b/arch/arm/kernel/iwmmxt.S
@@ -195,10 +195,10 @@ ENTRY(iwmmxt_task_disable)
@ enable access to CP0 and CP1
XSC(mrc p15, 0, r4, c15, c1, 0)
- XSC(orr r4, r4, #0xf)
+ XSC(orr r4, r4, #0x3)
XSC(mcr p15, 0, r4, c15, c1, 0)
PJ4(mrc p15, 0, r4, c1, c0, 2)
- PJ4(orr r4, r4, #0x3)
+ PJ4(orr r4, r4, #0xf)
PJ4(mcr p15, 0, r4, c1, c0, 2)
mov r0, #0 @ nothing to load
@@ -313,7 +313,7 @@ ENTRY(iwmmxt_task_switch)
teq r2, r3 @ next task owns it?
movne pc, lr @ no: leave Concan disabled
-1: @ flip Conan access
+1: @ flip Concan access
XSC(eor r1, r1, #0x3)
XSC(mcr p15, 0, r1, c15, c1, 0)
PJ4(eor r1, r1, #0xf)