diff options
| author | David Daney <ddaney@caviumnetworks.com> | 2009-05-12 12:41:53 -0700 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2009-06-17 11:06:26 +0100 |
| commit | 41f0e4d041aa30507a34998c29d0b7ac0bede277 (patch) | |
| tree | 7e84895b367ff6cfad682c6177c5ff706bb177c8 /arch | |
| parent | 95affdda9bfba0ac17025d48c622e1f30964e316 (diff) | |
| download | linux-41f0e4d041aa30507a34998c29d0b7ac0bede277.tar.bz2 | |
MIPS: Allow R2 CPUs to turn off generation of 'ehb' instructions.
Some CPUs do not need ehb instructions after writing CP0 registers.
By allowing ehb generation to be overridden in
cpu-feature-overrides.h, we can save a few instructions in the TLB
handler hot paths.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/mips/include/asm/cpu-features.h | 4 | ||||
| -rw-r--r-- | arch/mips/mm/tlbex.c | 3 |
2 files changed, 6 insertions, 1 deletions
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index c0047f861337..1cba4b2ffd1e 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -147,6 +147,10 @@ #define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \ cpu_has_mips64r1 | cpu_has_mips64r2) +#ifndef cpu_has_mips_r2_exec_hazard +#define cpu_has_mips_r2_exec_hazard cpu_has_mips_r2 +#endif + /* * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other * pre-MIPS32/MIPS53 processors have CLO, CLZ. For 64-bit kernels diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index d9a18b2b7f82..0e34faaadb5c 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -259,7 +259,8 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, } if (cpu_has_mips_r2) { - uasm_i_ehb(p); + if (cpu_has_mips_r2_exec_hazard) + uasm_i_ehb(p); tlbw(p); return; } |