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authoryangbo lu <yangbo.lu@nxp.com>2017-04-20 14:58:29 +0800
committerUlf Hansson <ulf.hansson@linaro.org>2017-04-28 14:53:13 +0200
commita627f025eb0534052ff451427c16750b3530634c (patch)
tree60a8e75c77fff90b506ddebdfa72a36348d001a5 /arch
parente145ac451eb68b51e0ede4c131bd5a539fb675b6 (diff)
downloadlinux-a627f025eb0534052ff451427c16750b3530634c.tar.bz2
mmc: sdhci-of-esdhc: limit SD clock for ls1012a/ls1046a
The ls1046a datasheet specified that the max SD clock frequency for eSDHC SDR104/HS200 was 167MHz, and the ls1012a datasheet specified it's 125MHz for ls1012a. So this patch is to add the limitation. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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