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| author | Max Filippov <jcmvbkbc@gmail.com> | 2015-09-24 23:20:46 +0300 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2015-11-02 18:02:51 +0300 |
| commit | 01618bded680573163403666d0546be536b22ac0 (patch) | |
| tree | cb566bdc9514682771e020d6c6b1501f768fee4b /arch/xtensa/include/asm/initialize_mmu.h | |
| parent | 5029615e25dc5040beb065f36743c127a8e51497 (diff) | |
| download | linux-01618bded680573163403666d0546be536b22ac0.tar.bz2 | |
xtensa: fix build for configs without cache options
- make cache-related assembly macros empty if core doesn't have
corresponding cache type;
- don't initialize cache attributes in instruction/data TLB entries if
there's no corresponding cache type.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'arch/xtensa/include/asm/initialize_mmu.h')
| -rw-r--r-- | arch/xtensa/include/asm/initialize_mmu.h | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/arch/xtensa/include/asm/initialize_mmu.h b/arch/xtensa/include/asm/initialize_mmu.h index e256f2270ec9..7a1e075969a3 100644 --- a/arch/xtensa/include/asm/initialize_mmu.h +++ b/arch/xtensa/include/asm/initialize_mmu.h @@ -161,7 +161,8 @@ #endif /* defined(CONFIG_MMU) && XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY */ -#if !defined(CONFIG_MMU) && XCHAL_HAVE_TLBS +#if !defined(CONFIG_MMU) && XCHAL_HAVE_TLBS && \ + (XCHAL_DCACHE_SIZE || XCHAL_ICACHE_SIZE) /* Enable data and instruction cache in the DEFAULT_MEMORY region * if the processor has DTLB and ITLB. */ @@ -175,14 +176,18 @@ 1: sub a9, a9, a8 2: +#if XCHAL_DCACHE_SIZE rdtlb1 a3, a5 - ritlb1 a4, a5 and a3, a3, a6 - and a4, a4, a6 or a3, a3, a7 - or a4, a4, a7 wdtlb a3, a5 +#endif +#if XCHAL_ICACHE_SIZE + ritlb1 a4, a5 + and a4, a4, a6 + or a4, a4, a7 witlb a4, a5 +#endif add a5, a5, a8 bltu a8, a9, 1b |