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authorIngo Molnar <mingo@kernel.org>2019-05-16 09:04:48 +0200
committerIngo Molnar <mingo@kernel.org>2019-05-16 09:04:48 +0200
commit00f5764dbb040188e5dce2cd9e648360886b045c (patch)
tree2dc969bb165a27a7cebdd1798b7a697243a790de /arch/xtensa/Kconfig
parent409ca45526a428620d8efb362ccfd4b1e6b80642 (diff)
parent5ac94332248ee017964ba368cdda4ce647e3aba7 (diff)
downloadlinux-00f5764dbb040188e5dce2cd9e648360886b045c.tar.bz2
Merge branch 'linus' into x86/urgent, to pick up dependent changes
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/xtensa/Kconfig')
-rw-r--r--arch/xtensa/Kconfig26
1 files changed, 20 insertions, 6 deletions
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index 35c8d91e6106..6ec1b75eabc5 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -253,12 +253,26 @@ config MEMMAP_CACHEATTR
region: bits 0..3 -- for addresses 0x00000000..0x1fffffff,
bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on.
- Cache attribute values are specific for the MMU type, so e.g.
- for region protection MMUs: 2 is cache bypass, 4 is WB cached,
- 1 is WT cached, f is illegal. For ful MMU: bit 0 makes it executable,
- bit 1 makes it writable, bits 2..3 meaning is 0: cache bypass,
- 1: WB cache, 2: WT cache, 3: special (c and e are illegal, f is
- reserved).
+ Cache attribute values are specific for the MMU type.
+ For region protection MMUs:
+ 1: WT cached,
+ 2: cache bypass,
+ 4: WB cached,
+ f: illegal.
+ For ful MMU:
+ bit 0: executable,
+ bit 1: writable,
+ bits 2..3:
+ 0: cache bypass,
+ 1: WB cache,
+ 2: WT cache,
+ 3: special (c and e are illegal, f is reserved).
+ For MPU:
+ 0: illegal,
+ 1: WB cache,
+ 2: WB, no-write-allocate cache,
+ 3: WT cache,
+ 4: cache bypass.
config KSEG_PADDR
hex "Physical address of the KSEG mapping"