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| author | Max Filippov <jcmvbkbc@gmail.com> | 2018-08-12 06:01:40 -0700 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2018-08-13 20:08:19 -0700 |
| commit | 7bb516ca5424e12b42124fab2906b6da9c81ba9c (patch) | |
| tree | 275dd23356eba62a81025221e23df3210a87a7be /arch/xtensa/Kconfig | |
| parent | fec3259c9f747c039f90e99570540114c8d81a14 (diff) | |
| download | linux-7bb516ca5424e12b42124fab2906b6da9c81ba9c.tar.bz2 | |
xtensa: rework noMMU cache attributes initialization
Marking default memory region as cached is not always sufficient and is
not flexible. Allow specifying cache attributes for the whole memory
address space with new config entry MEMMAP_CACHEATTR. Apply it after
cache initialization.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'arch/xtensa/Kconfig')
| -rw-r--r-- | arch/xtensa/Kconfig | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index d575e8701955..524b80722fd0 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -249,6 +249,23 @@ config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX If in doubt, say Y. +config MEMMAP_CACHEATTR + hex "Cache attributes for the memory address space" + depends on !MMU + default 0x22222222 + help + These cache attributes are set up for noMMU systems. Each hex digit + specifies cache attributes for the corresponding 512MB memory + region: bits 0..3 -- for addresses 0x00000000..0x1fffffff, + bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on. + + Cache attribute values are specific for the MMU type, so e.g. + for region protection MMUs: 2 is cache bypass, 4 is WB cached, + 1 is WT cached, f is illegal. For ful MMU: bit 0 makes it executable, + bit 1 makes it writable, bits 2..3 meaning is 0: cache bypass, + 1: WB cache, 2: WT cache, 3: special (c and e are illegal, f is + reserved). + config KSEG_PADDR hex "Physical address of the KSEG mapping" depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX && MMU |