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| author | Krish Sadhukhan <krish.sadhukhan@oracle.com> | 2020-09-17 21:20:37 +0000 |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2020-09-18 10:47:00 +0200 |
| commit | 75d1cc0e05af579301ce4e49cf6399be4b4e6e76 (patch) | |
| tree | 9f5f5e8e3cc8d5a99a4a0ff93d0fac01b5ac0812 /arch/x86/mm/pat | |
| parent | 5866e9205b47a983a77ebc8654949f696342f2ab (diff) | |
| download | linux-75d1cc0e05af579301ce4e49cf6399be4b4e6e76.tar.bz2 | |
x86/mm/pat: Don't flush cache if hardware enforces cache coherency across encryption domnains
In some hardware implementations, coherency between the encrypted and
unencrypted mappings of the same physical page is enforced. In such a
system, it is not required for software to flush the page from all CPU
caches in the system prior to changing the value of the C-bit for the
page. So check that bit before flushing the cache.
[ bp: Massage commit message. ]
Suggested-by: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: Krish Sadhukhan <krish.sadhukhan@oracle.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lkml.kernel.org/r/20200917212038.5090-3-krish.sadhukhan@oracle.com
Diffstat (limited to 'arch/x86/mm/pat')
| -rw-r--r-- | arch/x86/mm/pat/set_memory.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/mm/pat/set_memory.c b/arch/x86/mm/pat/set_memory.c index d1b2a889f035..40baa90e74f4 100644 --- a/arch/x86/mm/pat/set_memory.c +++ b/arch/x86/mm/pat/set_memory.c @@ -1999,7 +1999,7 @@ static int __set_memory_enc_dec(unsigned long addr, int numpages, bool enc) /* * Before changing the encryption attribute, we need to flush caches. */ - cpa_flush(&cpa, 1); + cpa_flush(&cpa, !this_cpu_has(X86_FEATURE_SME_COHERENT)); ret = __change_page_attr_set_clr(&cpa, 1); |